The present invention relates to a method of forming nickel silicide using a one step rapid thermal anneal and backend processing process.
Forming self-aligned suicides is well known in the semiconductor processing industry as a way of integrating low resistivity material on predefined regions of semiconductor structures that are being processed to form semiconductor devices. More specifically, self-aligned silicide processing is a method of reacting metal with silicon regions of a semiconductor structure to form silicide regions. Self-aligned silicides can be selectively formed on semiconductor structures without the necessity of patterning or etching the deposited silicide to define low resistively regions.
Titanium, cobalt, and nickel are among the metals that have been reacted with silicon materials to form self-aligned silicides on semiconductor structures. Titanium silicide can be formed on a semiconductor structure in a self-aligned manner. FIG. 1 shows an exemplary silicon substrate 10 with a polycrystalline silicon region 16 formed on the silicon substrate 10. Adjacent to the polycrystalline silicon region 16 are spacers 14. The spacers 14 can be an oxide, nitride, or other ceramic material. The silicon substrate 10 has active regions 12 that can be characterized as being doped silicon and may function as the source and drain of a transistor. In FIG. 2, a layer of titanium metal or titanium alloy 18 is deposited over the semiconductor structure of FIG. 1. The semiconductor structure of FIG. 2 then undergoes a first rapid thermal anneal (RTA) at temperatures ranging from 550xc2x0 C. to 750xc2x0 C. FIG. 3 shows the semiconductor structure of FIG. 2 after this first rapid thermal anneal. Some of the titanium metal or titanium alloy layer 18 reacts with the polycrystalline region 16 to form high resistivity silicide (TiSi2) regions 22. Additionally, some of the titanium layer 18 reacts with the silicon of the active region 12 to form high resistivity titanium silicide (TiSi2) region 20. During the first rapid thermal anneal, none of the titanium layer 18 reacts with the spacer 14. As silicide does not form on the spacers, the high resistivity titanium silicide regions 20, 22 are formed in a self-aligned manner, as it is not necessary to pattern or etch silicide off the spacers to define the titanium silicide regions 20, 22 on the polycrystalline region 16 and active region 12. It is undesirable to form silicide on the spacers 14 as this leads to bridging between the gate and the source/drain 12. Unreacted titanium in metal layer 19 of FIG. 3 is stripped away using conventional stripping techniques. FIG. 4 shows the semiconductor structure of FIG. 3 after the unreacted metal layer 19 is stripped away. The high resistivity titanium silicide regions 20, 22 remain integrated into the semiconductor structure after the wet strip of the unreacted metal 19. The semiconductor structure of FIG. 4 then undergoes a second rapid thermal anneal at temperatures ranging from 750xc2x0 C. to 900xc2x0 C. FIG. 5 shows the semiconductor structure of FIG. 4 after the second rapid thermal anneal where the high resistivity titanium silicide regions 20, 22 are reacted to form low resistivity silicide (TiSi2) regions 24, 26. The low resistivity silicide titanium regions 24 are formed on the polycrystalline silicon region 16 and low resistivity titanium silicide regions 26 are formed on the active region 12 of the silicon substrate 10.
There are several disadvantages of the above described two-step rapid thermal anneal process using titanium metal or titanium alloy to form low resistivity titanium silicide in a self-aligned manner. As semiconductor technology has advanced, it has become desirable for the dimensions of certain semiconductor structures to become smaller. For example, it is desirable for the polycrystalline region 16 and spacers 14 to be formed as small as possible on semiconductor substrate 10 to enhance performance of semiconductor devices using this type of structure. For example, transistors adopting this general semiconductor structure are designed and implemented with such small dimensions to enable the transistor to execute computer instructions at faster speeds. It is often necessary to form low resistivity titanium silicide regions on semiconductor structures to enable electrical interconnection of semiconductor components of a semiconductor device. Such exemplary regions are the active regions 12 and polycrystalline region 16 of FIG. 5. The use of titanium in a two step rapid thermal anneal process to form titanium silicide in a self-aligned manner is not effective with semiconductor structures of smaller dimensions because titanium metal or titanium alloy layer does not fully react with the small surfaces of silicon materials such as the polycrystalline silicon region 16 and active regions 12 of FIGS. 1-5. The reasoning behind this shortcoming of titanium in a self-aligned silicide processes is that the reaction of titanium with silicon materials are dominated by nucleation of the silicide and therefore the silicide does not form in a consistent manner. As exemplified in FIGS. 3-5, the reaction of titanium metal or titanium alloy with the silicon materials forms titanium silicide regions that are scattered, inconsistent, and not adequate for the formation of silicide regions in some semiconductor devices, such as transistors. As not all of the titanium metal or titanium alloy reacts on the silicon material surfaces of small semiconductor structures, the reaction of titanium with the silicon based material does not adequately lower the resistivity of the silicon based components of the semiconductor structure. Hence, the use of titanium does not adequately serve the objectives of forming silicides in a self-aligned manner for relatively small semiconductor structures. This limitation of the use of titanium in self-aligned suicides is often referred to as line width dependence.
Another disadvantage of the use of titanium metal or titanium alloy to form titanium suicides in a semiconductor structure is that the temperatures at which the first and second rapid thermal anneal undergo are relatively high. These high temperatures limit the designs of the semiconductor structures utilizing self-aligned suicides. High temperatures can induce stress on the semiconductor structure and can destroy the functionality of the semiconductor device. Other disadvantages of a two-step rapid thermal anneal process to form titanium silicide are also known.
Cobalt can also be reacted with silicon materials, such as polycrystalline silicon or a silicon substrate, to form self-aligned cobalt silicide regions in a semiconductor structure. FIG. 6, for example, shows a semiconductor substrate 10 with active regions 12 and a polycrystalline region 16 formed on the silicon substrate 10. Spacers 14 are formed on the silicon substrate 10 adjacent to the polycrystalline region 16. A layer of cobalt metal or cobalt alloy 28 is formed on the semiconductor structure of FIG. 6, as shown in FIG. 7. The semiconductor structure of FIG. 7 undergoes a first rapid thermal anneal at temperatures ranging from 450xc2x0 C. to 510xc2x0 C. FIG. 8 shows high resistivity cobalt silicide (CoSi) regions 30, 32 formed on the polycrystalline region 16 and the active regions 12 as a product of the first rapid thermal anneal process. Any unreacted cobalt metal or cobalt alloy 29 is wet stripped away using conventional stripping techniques. FIG. 9 shows the semiconductor structure of FIG. 8 with high resistivity cobalt silicide 30, 32 regions formed on the polycrystalline region 16 and the active region 12 of the substrate 10 after unreacted cobalt metal or cobalt alloy 29 is stripped away. No cobalt silicide is formed on the spacers 14; this feature exemplifies the self-alignment characteristic of self-aligned silicides. Further, the stripping does not strip away any of the formed cobalt silicide and only strips the unreacted cobalt metal or cobalt alloy 29. The semiconductor structure of FIG. 9 then undergoes a second rapid thermal anneal at temperatures ranging from 760xc2x0 C. to 840xc2x0 C. The second rapid thermal anneal reacts the high resistivity cobalt silicide regions 30, 32 to form low resistivity cobalt silicide (CoSi2) regions 34, 36. FIG. 10 shows low resistivity cobalt silicide regions 34, 36 formed on the polycrystalline silicon region and the active region 12 of the substrate 10.
There are several disadvantages of using cobalt metal or cobalt alloy reacted with silicon material to produce cobalt silicides in semiconductor processing. One disadvantage is that the two-step rapid thermal anneal process that is necessary to form low resistivity CoSi2 require relatively high temperatures. These relatively high temperatures may not be compatible or desirable with semiconductor processing of pre-existing components of the semiconductor structure. More particularly, these high temperatures may induce stress on other semiconductor components and/or diffuse materials of the existing semiconductor structure.
The use of nickel to form self-aligned silicides has been established using a one-step rapid thermal anneal process. FIG. 11, for example, shows a silicon substrate 10 with active regions 12. A polycrystalline silicon region 16 is formed on the silicon substrate 10 and spacers 14 are formed adjacent to the polycrystalline silicon region 16. A layer of nickel metal or nickel alloy is formed on the exemplary semiconductor structure of FIG. 11. FIG. 12, for example, shows a layer of nickel metal or nickel alloy 38 formed over the semiconductor structure of FIG. 11. A single rapid thermal anneal is conducted at temperatures ranging from 350xc2x0 C. to 700xc2x0 C. in order to react the nickel metal or nickel alloy to form a silicide with a relatively low resistance. FIG. 13, for example, depicts silicide regions 40, 42 formed from the single rapid thermal anneal. At the necessary rapid thermal anneal temperatures ranging from 350xc2x0 C. to 700xc2x0 C., undesirable bridging may occur between the nickel silicide formed on polycrystalline silicon region 16 and the nickel silicide formed on the active regions 12. The unreacted nickel in layer 4A is stripped, leaving the structure of FIG. 14.
There are certain concerns arising from the one-step rapid thermal anneal of nickel silicide. One concern is the relatively uncontrollable reaction and excessive formation of nickel silicide, which may cause the aforementioned bridging between the nickel silicide 40 formed on the polycrystalline silicon 16 and the nickel silicide 42 formed on the active regions 12, as seen in FIG. 14.
There is a need for a self-aligned silicide process that can accommodate a low thermal budget during processing and with a controlled silicidization reaction of metal or alloy with silicon material. Further, there is a need for a self-aligned silicide process that can combine processing steps during the fabrication of semiconductor devices.
These and other needs are met by embodiments of the present invention which provide a one-step temperature treatment process and backend processing to form self-aligned nickel silicide regions in a semiconductor structure. The present invention includes depositing a layer of nickel metal or nickel alloy on silicon material. At least a section of the nickel metal or alloy is reacted with at least a section of the silicon layer at a first temperature for a first period of time to form at least one high resistance nickel silicide layer. Unreacted nickel metal or nickel alloy is removed from the semiconductor structure leaving the at least one high resistance suicide layer integrated into the semiconductor structure. A dielectric layer is then deposited over the at least one high resistance nickel silicide layer. The dielectric layer and the at least one high resistance nickel silicide layer undergo a second temperature for a second period of time to form at least one low resistance nickel silicide layer.
The present invention has the advantage of producing silicide at a relatively low temperature. This feature reduces stress on other pre-existing semiconductor components of a semiconductor structure. This feature also allows the semiconductor processing of more complicated and useful semiconductor structures. Another advantage of the present invention is that the nickel metal layers react with the silicon based material layers in a controlled manner. This is an important and useful attribute as enough nickel silicide is reacted such that line width dependence is not an obstacle and bridging between silicide regions formed on the same semiconductor structure is prevented. Further, the present invention has the advantage of combining the processing of the high resistance nickel silicide layer and processing of the dielectric layer in a single step of undergoing a second temperature for a second period of time.
The foregoing and other features, aspects, and advantages of the present invention will become more apparent from the following detailed description of the present invention taken in conjunction with the accompanying drawings.